The invention generally relates to controlling signal states and leakage current during a sleep mode.
A computer (a palm top computer or notebook computer, as examples) may have at least one sleep mode to conserve power when the computer is not currently being used. In this sleep mode, one or more voltage supplies to a particular semiconductor package, or chip, of the computer may be cut off. For example, in a microprocessor of the computer, the low voltage core supply of the microprocessor may be shut off during the sleep mode while the high voltage core supply is left on to supply power to input/output (I/O) circuitry of the microprocessor.
The I/O circuitry is kept in a low power state during the sleep mode (instead of being shut down) to keep the external interface to the microprocessor enabled. For example, during the sleep mode, some output terminals of the I/O circuitry need to be held in specific high or low logic states while the core circuitry is shut off; and some input terminals of the I/O circuitry need to be enabled to permit a wakeup of the microprocessor from the sleep mode. However, some of this I/O circuitry may also need a low voltage supply to function properly. Thus, because the low voltage core supply is cut off, the microprocessor may include voltage regulators to generate the low supply voltages for the I/O circuitry from the high voltage core supply.
As a more specific example, FIG. 1 depicts an I/O driver 5 that includes an I/O control circuit 10, a level shifter 12, buffer/reset circuitry 14 and a complementary output driver 18. The I/O control circuit 10 receives an input signal via input terminals 7. During a non-sleep mode, the I/O control circuit 10 furnishes a signal on its output terminal indicative of the voltage across the pins 7. The level shifter 12 translates the logic level of the signal from the I/O control circuit 10 and forms complementary signals (called PULLUP and PULLDOWN) to drive output circuitry 18 through the buffer/reset circuitry 14. An output terminal 19 of the output circuitry 18 provides an output signal indicative of the logic signal that appears across the input terminals 7.
During the sleep mode, circuitry of the I/O driver 5, such as the I/O control circuit 10 and the buffer/reset circuitry 14 may set the output signal of the driver 5 to a predetermined logic level or possibly even tri-state the output terminal 19. However, to power some of its low voltage circuitry during the sleep mode, the I/O driver 5 may include a voltage regulator 25 to replace the low voltage core supply that is cut off during the sleep mode.
For example, the I/O driver 5 may include approximately three different regions according to their power requirements: a region 20 in which components are powered via a low voltage core supply voltage (called VL), a region 22 in which components are powered via the VL supply voltage and a higher voltage core supply voltage (called VH); and a region 24 in which the components are powered via the VH supply voltage. As depicted in FIG. 1, as an example, the I/O control circuit 10 may be located in the region 20; the level shifter 12 may be located in the region 22; and the buffer/reset circuitry 14 and output driver 18 may be located in the region 24. As an example, the VL supply voltage may be approximately 1 volt, and the VH supply voltage may be approximately 3.3 volts. The I/O driver 5 uses the voltage regulator 25 to generate the VL supply voltage for the regions 20 and 22, as depicted in FIG. 1.
A difficulty with the above-described arrangement is that the die space that is consumed by the I/O driver 5 is made significantly bigger with the inclusion of the voltage regulator 25. Furthermore, the use of the voltage regulator 25 increases the power that is dissipated during the sleep mode. An additional difficulty with the operation of such circuitry when a power supply is cut off, is the power dissipation that occurs due to leakage currents.
Thus, there is a continuing need for an arrangement to address one or more of the above-stated problems.